>>
and >>>
in verilog/system verilog? I know that tests for only 1 and 0, while tests for 1, 0, X, Z. So how is that similar to the shift operator?>>>
performs sign extension.>>
is a binary logical shift, while >>>
is a binary arithmetic shift.>>>
) - shift right specified number of bits, fill with value of sign bit if expression is signed, otherwise fill with zero,<<<
) - shift left specified number of bits, fill with zero.<<
, >>
) always fill the vacated bit positions with zeroes.